Advanced packaging

Advanced packaging is a set of techniques for combining several chips (chiplets), memory stacks, and even optics into a single high-performance package, instead of relying on one large monolithic chip. Methods like 2.5D interposers (CoWoS) and 3D stacking shorten signal paths and add bandwidth, making them essential for AI accelerators and data centers.

What advanced packaging is, in plain terms

For decades, chipmakers improved performance mainly by shrinking transistors (Moore's Law). As that scaling gets harder and more expensive, **advanced packaging** has become a second lever: instead of building one giant chip, you split the design into smaller pieces called **chiplets** and assemble them tightly together inside a single package. The package itself becomes part of the performance story, not just protective plastic around a die. The goal is to get many chips talking to each other with huge bandwidth, low power, and short distances, without depending on the newest transistor node for every part.

How it works: 2.5D, 3D, and chiplets

In **2.5D packaging**, multiple dies sit side by side on a **silicon interposer** (a thin slab packed with fine wiring) that routes far more connections than a normal circuit board could. In **3D packaging**, dies are stacked vertically and connected with **through-silicon vias (TSVs)** drilled through the silicon, plus increasingly with **hybrid bonding** (direct copper-to-copper joins) for the densest links. A modern AI accelerator typically combines a logic die with several stacks of **high-bandwidth memory (HBM)** on one interposer. **TSMC's CoWoS** (Chip-on-Wafer-on-Substrate) is the best-known 2.5D platform; its **SoIC** is a 3D stacking technology.

Why it matters for AI and data centers

AI training and inference are bottlenecked by **memory bandwidth and data movement**, not just raw compute. Advanced packaging lets a GPU or accelerator sit right next to multiple HBM stacks, feeding the compute engine far faster than separate chips on a board ever could. It also improves performance-per-watt, which matters enormously when data centers run tens of thousands of accelerators. This is why packaging capacity, especially CoWoS, has become a real supply constraint on AI hardware: TSMC roughly doubled CoWoS output in 2025 and is targeting around 120,000-130,000 wafers per month of capacity by the end of 2026.

Where it sits in the supply chain

Advanced packaging happens at the **back end** of chip manufacturing, after wafers are fabricated. Three groups do it: **foundries** like TSMC (which now offers packaging alongside fabrication), specialist **OSATs** (Outsourced Semiconductor Assembly and Test) such as Amkor and ASE, and **materials/equipment** suppliers who provide substrates, interposers, lasers, and bonding tools. A growing frontier is **glass substrates** and panel-level packaging, where companies like LPKF supply laser-based glass structuring (its LIDE process) for next-generation interposers. The line between "making" and "packaging" a chip is blurring.

Who the key players are

**TSMC (TSM)** dominates leading-edge 2.5D/3D packaging via CoWoS and SoIC and supplies most AI accelerators. **Amkor (AMKR)** is the largest US-headquartered OSAT and the world's #2 overall; on June 16, 2026 it announced a 10-year partnership with TSMC to provide packaging and test capacity, including expanded Arizona facilities. **ASE Technology (ASX)** is the world's largest OSAT and a major outsourcing partner for spillover CoWoS-style work. **LPKF (LPK)** is an equipment/materials supplier positioned in glass-based advanced packaging. Intel (Foveros, EMIB) and Samsung are also significant, alongside substrate makers and HBM suppliers like SK hynix, Samsung, and Micron.

What's changing now

Three shifts stand out. First, **outsourcing**: TSMC is handing a meaningful slice of CoWoS demand to OSATs (Amkor and SPIL) to meet AI orders. Second, **co-packaged optics (CPO)**, where optical engines are packaged right next to switch and accelerator ASICs to move data with light instead of copper. NVIDIA's Quantum-X and Spectrum-X switches and Broadcom's CPO efforts are early examples, with large-scale data-center deployment expected around 2028-2030. Third, a push toward **glass substrates, panel-level packaging, and hybrid bonding** to keep scaling bandwidth and package size as chips get bigger.

Frequently asked

What is the difference between advanced packaging and a normal chip package?

A traditional package mostly protects a single die and connects it to a board. Advanced packaging actively integrates multiple chiplets, memory stacks, and sometimes optics into one high-bandwidth package, making the package part of the chip's performance rather than just an enclosure.

What is CoWoS?

CoWoS (Chip-on-Wafer-on-Substrate) is TSMC's leading 2.5D packaging technology. Known-good dies, typically a logic chip plus HBM memory stacks, are placed on a silicon interposer and then mounted on a substrate. It is the dominant packaging method behind today's AI GPUs and accelerators.

Why is advanced packaging a bottleneck for AI chips?

AI accelerators need their logic die packaged together with multiple HBM stacks on an interposer, and that packaging capacity (especially CoWoS) is limited and slow to expand. When demand for AI chips spikes, packaging capacity, not just transistor fabrication, becomes the constraint.

What is the difference between 2.5D and 3D packaging?

In 2.5D, chips sit side by side on an interposer that wires them together horizontally. In 3D, chips are stacked vertically and connected through the silicon itself using through-silicon vias and, increasingly, hybrid bonding for denser connections.

How does advanced packaging relate to co-packaged optics?

Co-packaged optics (CPO) is an emerging form of advanced packaging that places optical engines directly beside switch or accelerator chips, replacing some copper links with light to cut power and boost bandwidth. Broad data-center deployment is expected roughly between 2028 and 2030.

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